
module regfile(
    input wire clk,
    input wire [4:0] rs1,
    input wire [4:0] rs2,
    input wire [4:0] rd,
    input wire [31:0] regdata,
    input wire wer,
    output wire [31:0] rv1,
    output wire [31:0] rv2,
    output wire [31:0] x31
);

    // Initialize 32x32-bit register array to zero
    reg [31:0] register [31:0];
    integer i;
    initial begin
            register[0] = 32'b0;
            register[1] = 32'b0;
            register[2] = 32'h10000;
        for (i = 3; i < 32; i = i + 1) begin
            register[i] = 32'b0;
        end
    end

    // Handle write operations
    always @(posedge clk) begin
        if (wer && rd != 0) begin
            register[rd] <= regdata;
        end
    end

    // Handle read operations for rs1 and rs2
    assign rv1 = (rs1 == 0) ? 32'b0 : register[rs1];
    assign rv2 = (rs2 == 0) ? 32'b0 : register[rs2];

    // Continuous output of register 31
    assign x31 = register[31];

endmodule


